Semiconductor devices typically include multiple individual components formed on or within a substrate. Such devices often comprise a high density section and a low density section. For example, as illustrated in prior art FIG. 1, a memory device such as a flash memory 10 comprises one or more high density core regions 12 and a low density peripheral portion 14 on a single substrate 16. The high density core regions 12 typically consist of at least one M.times.N array of individually addressable, substantially identical memory cells and the low density peripheral portion 14 typically includes input/output (I/O) circuitry and circuitry for selectively addressing the individual cells (such as decoders for connecting the source, gate and drain of selected cells to predetermined voltages or impedances to effect designated operations of the cell such as programming, reading or erasing).
The memory cells within the core portion 12 are coupled together in a circuit configuration, such as the configuration illustrated in prior art FIG. 2. Each memory cell 20 has a drain 22, a source 24 and a stacked gate 26. Each stacked gate 26 is coupled to a word line (WL0, WL1, . . . , WLn) while each drain 22 is coupled to a bit line (BL0, BL1, . . . , BLn). Lastly, each source 24 is coupled to a common source line CS. Using peripheral decoder and control circuitry, each memory cell 20 can be addressed for programming, reading or erasing functions.
Prior art FIG. 3 represents a fragmentary cross section diagram of a typical memory cell 20 in the core region 12 of prior art FIGS. 1 and 2. Such a cell 20 typically includes the source 24, the drain 22 and a channel 28 in a substrate 30; and the stacked gate structure 26 overlying the channel 28. The stacked gate 26 further includes a thin gate dielectric layer 32 (commonly referred to as the tunnel oxide) formed on the surface of the substrate 30. The stacked gate 26 also includes a polysilicon floating gate 34 which overlies the tunnel oxide 32 and an interpoly dielectric layer 36 overlies the floating gate 34. The interpoly dielectric layer 36 is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers 36a and 36b sandwiching a nitride layer 36c. Lastly, a polysilicon control gate 38 overlies the interpoly dielectric layer 36. The control gates 38 of the respective cells 20 that are formed in a lateral row share a common word line (WL) associated with the row of cells (see, e.g., prior art FIG. 2). In addition, as highlighted above, the drain regions 22 of the respective cells in a vertical column are connected together by a conductive bit line (BL). The channel 28 of the cell 20 conducts current between the source 24 and the drain 22 in accordance with an electric field developed in the channel 28 by the stacked gate structure 26.
According to conventional operation, the flash memory cell 20 operates in the following manner. The cell 20 is programmed by applying a relatively high voltage V.sub.G (e.g., approximately 12 volts) to the control gate 38 and a moderately high voltage V.sub.D (e.g., approximately 9 volts) to the drain 22 in order to produce "hot" (high energy) electrons in the channel 28 near the drain 22. The hot electrons accelerate across the tunnel oxide 32 and into the floating gate 34 and become trapped in the floating gate 34 since the floating gate 34 is surrounded by insulators (the interpoly dielectric 36 and the tunnel oxide 32). As a result of the trapped electrons, the threshold voltage of the cell 20 increases by about 3 to 5 volts. This change in the threshold voltage (and thereby the channel conductance) of the cell 20 created by the trapped electrons is what causes the cell to be programmed.
To read the memory cell 20, a predetermined voltage V.sub.G that is greater than the threshold voltage of an unprogrammed cell, but less than the threshold voltage of a programmed cell, is applied to the control gate 38. If the cell 20 conducts, then the cell 20 has not been programmed (the cell 20 is therefore at a first logic state, e.g., a zero "0"). Likewise, if the cell 20 does not conduct, then the cell 20 has been programmed (the cell 20 is therefore at a second logic state, e.g., a one "1"). Consequently, one can read each cell 20 to determine whether it has been programmed (and therefore identify its logic state).
In order to erase the flash memory cell 20, a relatively high voltage V.sub.S (e.g., approximately 12 volts) is applied to the source 24 and the control gate 38 is held at a ground potential (V.sub.G =0), while the drain 24 is allowed to float. Under these conditions, a strong electric field is developed across the tunnel oxide 32 between the floating gate 34 and the source region 22. The electrons that are trapped in the floating gate 34 flow toward and cluster at the portion of the floating gate 34 overlying the source region 22 and are extracted from the floating gate 34 and into the source region 22 by way of Fowler-Nordheim tunneling through the tunnel oxide 32. Consequently, as the electrons are removed from the floating gate 34, the cell 20 is erased.
During the processing of the core portion 12 having a circuit configuration as illustrated in prior art FIG. 2 and a structure as illustrated in prior art FIG. 3, a problem sometimes occurs involving poly stringers. The manner in which poly stringers are formed is illustrated in conjunction with prior art FIGS. 4a-7. Poly stringers result from (among other things) imperfect anisotropic etching of the floating polysilicon gate 34 (when delineating memory cells 20 along a given word line) and the subsequent shielding of some polysilicon material by an ONO "fence."
An ideally anisotropically etched polysilicon gate 40 is illustrated in prior art FIG. 4a with an oxide-nitride-oxide (ONO) layer 42 overlying the gate 40. Note that at regions 44 and 46 the ONO layer 42 exhibits a film thickness "X" while at a region 48 (along the sidewalls of the gate 40) the ONO layer 42 exhibits a film thickness "Y", wherein X&lt;&lt;Y. Consequently, as illustrated in prior art FIG. 4b, when the ONO layer 42 is subsequently etched, removing a film thickness of X, an ONO fence 50 is left along the sidewalls 52 and 54 of the polysilicon gate 40. Subsequently, when portions of the polysilicon gate 40 are again etched to define the various word lines for the memory device, the ONO fence 50 remains, as illustrated in prior art FIG. 4c.
The manner in which the ONO fence 50 remains after the second etching of the polysilicon gate 40 may best be understood in its macroscopic context, as illustrated in prior art FIG. 5. In FIG. 5, the polysilicon gate 40 rests on the substrate 30 (actually, it rests on a thin tunnel oxide which, although not shown for simplicity, overlies the substrate 30). The ONO fence 50 remains along the sidewalls 52 and 54 in the regions 60 and 62 where a first word line (WL1) and a second word line (WL2) are formed in a manner similar to prior art FIG. 4b. (Note that the additional layers that make up the stacked gate structure 26 are not shown in prior art FIG. 5 for the sake of simplicity.) In an etched region 64, which delineates the regions 60 and 62 (and consequently the word lines WL1 and WL2) the ONO fence 50 also remains in a manner similar to prior art FIG. 4c.
As long as the initial etching of the polysilicon gate 40 (which delineates cells 20 along a single word line) occurs in an ideally anisotropic manner, as illustrated in prior art FIGS. 4a-4c and FIG. 5, no poly stringers are formed during the second etching of the gate 40 (which delineates separate word lines). It is well known, however, that anisotropic etch processes do not repeatably provide ideally anisotropic profiles. Instead, most anisotropic etch processes provide non-ideal profiles in the range of about 85-95.degree. (wherein 90.degree. is ideal). A non-ideal anisotropic etch profile 65 is illustrated in prior art FIG. 6a. When the ONO layer 42 of FIG. 6a is etched, an angled ONO fence 68 is left on the sloped sidewalls 70 and 72 of the polysilicon gate 65 because the region 66 has a film thickness "Z" along the sidewalls 70 and 72 that is thicker than the film thickness "X". Consequently, the angled ONO fence 68 remains, as illustrated in prior art FIG. 6b.
When the polysilicon gate 65 is subsequently etched (in an anisotropic manner via, e.g., reactive ion etching (RIE)), as illustrated in prior art FIGS. 6b and 6c, the angled ONO fence 68 shields a portion of the polysilicon gate 65, resulting in remnants 74 and 76 of polysilicon, which are the poly stringers. Transposing the non-ideally anisotropic polysilicon gate 65 and the resulting poly stringers 74 and 76 of FIGS. 6a-6c into their macroscopic context (as illustrated in prior art FIG. 7), it is clear that the poly stringers 74 and 76 pose a substantial reliability problem since the poly stringers 74 and 76 in the etched region 64 can short out the word lines in regions 60 and 62, respectively. That is, instead of the etched region 64 electrically isolating the word lines in regions 60 and 62 from one another, the poly stringers 74 and 76 (which are conductive) span the etched region 64, shielded by the angled ONO fence 68 and cause the gates 65 in the regions 60 and 62 to be shorted together.
Consequently, there is a strong need in the art to form memory devices without poly stringers and thereby reduce reliability problems due to shorted word lines.